1. Field of the Invention
This invention relates to two-dimensional rasterization systems, particularly as applied to E-beam lithography, used to produce masks for integrated circuit-fabrication or to directly expose a silicon wafer.
2. Discussion of Background
E-beam lithography systems are used in the manufacturing of integrated circuits. These systems accept pattern data from a magnetic disk or tape and form images from that information by selectively exposing, with a finely focused electron beam, an electron-sensitive resist material covering the substrate. After exposure, the substrate is removed from the system and is developed by an etching process. The resolution of the E-beam system defines the smallest feature that can be formed and, therefore, affects the scale of integration that the system is capable of supporting.
A raster scanning scheme is used to write a pattern with the E-beam. The beam scans in one axis over the area to be exposed. Motion in the other, perpendicular, axis is achieved by moving the substrate. FIG. 1 illustrates the raster-scan routine. Sweeping the beam over the substrate in a series of parallel stripes is one aspect of the basic writing scheme.
Another aspect is the problem of switching the beam on and off in the appropriate places as it sweeps in order to obtain the exposure contrast between the pattern features and the background. This can be envisioned as if a stripe that is written is presented as a dot matrix or grid in which the pattern features are formed when positions in the grid are exposed by the beam and the background then becomes all of the positions that are left unexposed. This is illustrated in FIG. 1. Each grid position is called an address, and the spot size (i.e., the diameter of the beam at the writing surface) is equal to the address size, which is the length of one side of the address (addresses are square). The beam is driven by the bit-map of the pattern which is a binary numerical representation of a stripe to be written. For each address in the stripe there is a bit position in the bit-map. If the bit position holds a 1, the address is exposed, while it is left unexposed if the bit position holds a 0. FIG. 2 illustrates the bit-map correspondence of a pattern feature.
In preparation for writing a stripe, the E-beam system extracts from the pattern data the information for the stripe and constructs the bit-map. The stripe data is a collection of Electron Beam Exposure System (EBES) figures. FIG. 3 illustrates the repertoire of EBES figures. In standard EBES format, there is a figure entry every time a figure appears in a stripe, while in extended EBES format, figures are repeated many times and there is only one figure entry which includes the repetition factor and the interval of repetition. The extended EBES format offers a dramatic compression of the input data thus making possible the writing of very large scale integrated circuits.
When an E-beam system is used commercially for fabrication of masks and reticles, a performance parameter of major importance is throughput in terms of masks or reticles produced per unit time. This performance parameter is directly affected by the time the system requires to convert pattern data into a bit-map.
Currently there are no E-beam systems capable of writing reticles in real time, i.e., converting pattern data into a bit-map as fast as the beam scans a stripe driven by the bit-map. The lack of real-time writing results in high data handling overhead and low system throughput because exposure and bit-map conversion are sequential processes. Overhead times of 16 to 1 have been reported for E-beam systems currently operating in the field. This overhead is expected to dramatically increase as design of larger scale integrated circuits evolves. An attempt to decrease the bit-map conversion of pattern data by restricting the input data only to rectangles or EBES figures with 45.degree. angles offers some improvement but is viewed as highly undesirable.
Existing pattern data handling systems employed by E-beam systems operating in the field rely on a special purpose uniprocessor to perform the pattern data to bit-map conversion. FIG. 4 illustrates the block diagram of the subsystem that performs the pattern data handling. Pattern data stored on a tape 1 are converted to appropriate data format by host computer 2. A bit pattern to be exposed is stored in a disk 1 in the form of segment stripe data. Each segment stripe contains figure data in EBES format. The figures in a segment stripe are randomly placed, and the address of their left most corner indicates their location in the segment stripe. Data contained in a segment stripe is transferred from the disk via the host computer 2 to the pattern memory 4. The special purpose processor 5 accesses data from the pattern memory, one figure at a time, converts it to bit-map form and writes it into the bit-map memory 6.
The conversion of the EBES figures into bit-map representation is based on a polygon rasterization algorithm which is very inefficient when the figures are trapezoids and also requires a read-modify-write operation when the converted figure is stored in the bit-map memory. This is a very time consuming operation which adversely affects the processor throughput as will be shown shortly. After all the figures in the segment stripe have been processed, the host computer 2 initiates the data transfer from the bit-map memory 4 to the blanking register 7 and consequently to the beam. The data transfer to the register 7 takes place under the control of the special purpose processor 5, and it occurs on a word (i.e., 16-bits) by word basis while the output of the blanking register is a single bit at a time. During writing (i.e., loading the blanking register 7 with bit-map data), the special purpose processor 5 does not process data from another segment stripe. The beam is forced to an idle state as soon as the current segment stripe has been exposed and remains idle for as long as it takes the special purpose processor 5 to produce the bit-map of the next segment stripe. The sequencing of these events is a source of time overhead that has a negative impact on performance of the E-beam system in terms of throughput
An example illustrating the writing procedure of a single pattern and of an array of identical patterns is shown in FIGS. 5-8. The E-beam scanning is synchronized with the moving stage that holds the substrate. In the case of a single pattern, when writing of one segment stripe is complete, the motion of the stage is reversed and the next segment stripe is written in the opposite direction (FIG. 5) when the bit-map data becomes available. In the case of an array of identical patterns, the first segment stripe is written into all the array elements before the computation of the next segment stripe begins. The writing of a segment stripe of alternate rows of the array occurs in opposite directions as shown in FIGS. 6-8. This system takes advantage of the identical patterns in the array to reduce the ratio of figure to bit-map conversion time versus writing time, since the bit-map of a segment stripe is computed once and is then written into all the array elements. The system's performance, even in this case, is far from approaching real-time writing, and it is further linearly deteriorated in case the patterns in the array are not identical, which is often the case.
U.S. Pat. No. 4,433,384 to Berrian et al discloses a pattern data handling system for an electron beam exposure system. Berrian et al attempt to obtain writing and concurrent data conversion using a five processor system to perform the figure to bit-map conversion. In the Berrian et al system, the pattern conversion is performed by four processors with their own bit-map memory while the fifth is managing the data transfer from four bit-map memories to the shift register that drives the beam blanker. The overall architecture is, in principal, the same as in the case of a uniprocessor, the only difference being the four copies of the uniprocessor which perform in parallel. Figures are converted using the polygon writing algorithm, as in the uniprocessor case, and the data handled is standard EBES only (i.e., no figure repetition is allowed). When figures are converted to a bit-map, the bit-map has to be stored in memory through a read-modify-write operation. The segment stripes handled by this system are 1024 bits by 244 bits, and the maximum number of figures the system can handle is 50,000.
Although the Berrian et al system configuration offers some throughput improvements compared to the uniprocessor system, it also has some distinct disadvantages. All four processors access the same pattern memory which implies the existence of memory dependencies. That is, a memory request cannot be served before the request currently under service is completed. The pattern memory is a single port memory and it cannot be filled with new stripe data while the current stripe data is being processed, thus lowering the overall system throughput. The involvement of the Nova-4 Data General computer in controlling the bit-map transfer to the blanking circuits and its handshaking with the four processors adversely affects the system performance due to the differential in speed between the Nova-4 and the AMD2901. Finally, the amount of data this configuration can process on per stripe basis is significantly lower than the amount of data encountered in today's very large scale integrated circuits (VLSI), and therefore, the system can only be used if the data structures are modified (i.e., segment stripes are divided in smaller entities), which poses serious complications for other parts of the E-beam data handling system.
Other U.S. patents of interest are U.S. Pat. Nos. 3,900,737; 4,145,597; 4,147,937; 4,258,265; 4,259,724; 4,267,456; 4,280,186; 4,291,231; 4,387,433; 4,433,384; 4,445,039; 4,477,729; 4,489,241; 4,498,010; 4,511,980; 4,532,598; and 4,538,232.